FIG. 13 is a diagram illustrating a prior art differential amplifier having a single phase input and two phase output. In the figure, reference numeral 1 designates a field effect transistor (hereinafter referred to as FET) Q1 having its gate as an input terminal. Reference character IN designates an input terminal to which a signal to be amplified is input, and this input terminal is connected to a gate of the FET Q1. Reference numeral 2 designates an FET Q2 whose gate terminal is connected to a minus side terminal of the reference voltage source V.sub.REF and a source terminal thereof is commonly connected to the source terminal of the FET Q1. A load resistance R1 is connected to a drain terminal of the FET Q1. A load resistance R2 is connected to a drain terminal of the FET Q2. An anode electrode of a level shift diode D1 is connected to the ground and a cathode electrode of the level shift diode D1 is connected to the other ends of the load resistances R1 and R2. A constant current source FET Q3 has its gate terminal and source terminal both connected to the power supply V.sub.SS and a drain terminal connected to the connection node of the source electrodes of the FET Q1 and FET Q2. Reference character V.sub.REF designates a reference voltage source whose plus side terminal is connected to the ground and the minus side terminal of the reference voltage source V.sub.REF is connected to the gate terminal of the FET Q2. Reference character OUT designates an output terminal connected to the drain terminal of the FET Q2. Reference character OUT designates an output terminal connected to the drain terminal of the FET Q1. An amplified signal of the same phase as that of the signal input to the input terminal IN is output from the output terminal OUT and an amplified signal of the reverse phase to that of the signal input to the input terminal IN is output from the output terminal OUT. A differential amplifier is constructed by the above described circuit elements FET Q1, FET Q2, R1, R2, D1 and FET Q3.
FIGS. 14(a)-14(d) show timing waveforms of the voltage applied to respective terminals and the current flowing through respective FETs in the prior art differential amplifier shown in FIG. 13.
FIG. 14(a) is a diagram for explaining the circuit parameters of the prior art differential amplifier shown in FIG. 13 which are established so as to obtain the timing waveforms of FIGS. 14(b)-14(d).
In the graph shown in FIG. 14(b), the broken line shows the input voltage V.sub.IN input to the input terminal IN, the dotted line shows the value of the power supply V.sub.REF, and a solid line shows the drain terminal voltage V.sub.D3 of the FET Q3.
The input signal is -3.6.+-.0.5 V, the reference voltage source V.sub.REF is -3.6 V, the power supply V.sub.SS is -5.2 V, and the period is 500 ps(=0.5 ns).
The second stage graph shown in FIG. 14(c) shows the two phase output waveforms, and the broken line shows the voltage waveform V.sub.OUT of the reverse phase output OUT, and the solid line shows the waveform V.sub.OUT of the positive phase output OUT.
The bottom graph shown in FIG. 14(d) shows current waveforms of the drain currents I1, I2 and I3 of the respective FETs Q1, Q2 and Q3, and the solid line shows a current waveform of I1, a broken line shows a current waveform of I2, and the dotted line shows a current waveform of I3.
A description is given of the operation. When the input voltage input to the terminal IN is at low level (-3.6-0.5 V), the gate source terminal voltage V.sub.GS1 of the FET Q1 becomes V.sub.GS1 .div.V.sub.TH (=0.1 V) for the threshold voltage V.sub.TH and the FET Q1 is turned off. On the other hand, since the FET Q2 has a gate source terminal voltage of V.sub.GS2 .div.1 V (&gt;&gt;V.sub.TH), the FET Q2 is turned on, whereby a current of I2.div.I3 (the difference between I2 and I3 in the figure is a gate source current I.sub.GS2 of the FET Q2) flows therethrough. Next, when the input voltage is at high level (-3.6+0.5 V), V.sub.GS1 .div.1 V and the FET Q1 is turned on, whereby a current of I1.div.I3 (the difference between I1 and I3 in the figure is a gate source current I.sub.GS2 of the FET Q2) flows therethrough, thereby turning off the FET Q2.
Thus when the FET Q2 is turned off, it should be V.sub.GS2 =V.sub.TH. However, since the gate terminal of the FET Q2 is fixed to a constant voltage (V.sub.REF =-3.6 V), the drain terminal voltage V.sub.D3 of the FET Q3 serving as a constant current source is raised, thereby turning off the FET Q2.
Accordingly, the drain terminal voltage of the FET Q3 changes with a constant amplitude of .DELTA.V.sub.D3 .div.(input voltage amplitude )/2-V.sub.TH. The current flowing through the FET Q3 serving as a constant current source changes (by .DELTA.I3) in proportional to the change .DELTA.V.sub.D3 of the drain terminal voltage. Since .DELTA.V.sub.D3 =.DELTA.I3.times.R.sub.DS3 (the impedance between drain and source of the FET Q3), when the R.sub.DS3 is large, i.e., several tens of k.OMEGA., the change in the current is quite small, i.e., negligible. However, when a conventional GaAs MESFET is employed, the impedance thereof is relatively small, i.e., several hundreds to 1 k.OMEGA., and the change in the current cannot be ignored. In the graphs of FIGS. 14(b) to 14(d), the drain terminal voltage of the FET Q3 changes by .DELTA.V.sub.D3 =about 0.4 V, and, since the impedance R.sub.DS3 of the FET Q3 is about 2 k.OMEGA., the current changes by about .DELTA.I3.div.0.2 mA.
By this influence, a difference of I1-I2=(1.77 mA.sub.p-p)-(1.64 mA.sub.p-p)=0.13 mA between the drain current amplitudes of the FET Q1 and the FET Q2 is generated, and a difference is generated in the output voltage amplitude at both of the output terminals OUT and OUT by the product of the current amplitude difference and the load resistance R1 or R2, i.e., (I1-I2).multidot.R1=0.13 mA.times.600.OMEGA.=78 mV (this approximately coincides with the difference of 80 mV between V.sub.OUT =1.05 V.sub.p-p and V.sub.OUT =0.97 V.sub.p-p.)
In the prior art differential amplifier circuit constructed as described above, the operation mechanism of turning on and off the FET Q1 and the FET Q2 is different depending on whether the input signal voltage is high or low. In the FET Q3 having a small drain-source impedance, there is generated a difference between the signal currents I1 and I2 flowing therethrough, thereby producing a difference in the output voltage amplitude.